PIC16LF18854 Datasheet, PDF (57/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-13: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6
CPU CORE REGISTERS; see Table 3-2 for specifics
30Ch
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
30Dh
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
30Eh
CCP1CON
EN
—
OUT
FMT
MODE<3:0>
30Fh
CCP1CAP
—
—
—
—
—
CTS<2:0>
310h
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
311h
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
312h
CCP2CON
EN
—
OUT
FMT
MODE<3:0>
313h
CCP2CAP
—
—
—
—
—
CTS<2:0>
314h
CCPR3L
Capture/Compare/PWM Register 3 (LSB)
315h
CCPR3H
Capture/Compare/PWM Register 3 (MSB)
316h
CCP3CON
EN
—
OUT
FMT
MODE<3:0>
317h
CCP3CAP
—
—
—
—
CTS<3:0>
318h
CCPR4L
Capture/Compare/PWM Register 4 (LSB)
319h
CCPR4H
Capture/Compare/PWM Register 4 (MSB)
31Ah
CCP4CON
EN
—
OUT
FMT
MODE<3:0>
31Bh
CCP4CAP
—
—
—
—
CTS<3:0>
31Ch
CCPR5L
Capture/Compare/PWM Register 5 (LSB)
31Dh
CCPR5H
Capture/Compare/PWM Register 5 (MSB)
31Eh
CCP5CON
EN
—
OUT
FMT
MODE<3:0>
31Fh
CCP5CAP
—
—
—
—
CTS<3:0>
Legend:
Note 1:
2:
x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Register present on PIC16F18855/75 devices only.
Unimplemented, read as ‘1’.
Value on:
POR, BOR
Value on all
other Resets
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000
xxxx xxxx
xxxx xxxx
0-00 0000
---- 0000