PIC16LF18854 Datasheet, PDF (140/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-9: PIE7: PERIPHERAL INTERRUPT ENABLE REGISTER 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
SCANIE
CRCIE
NVMIE
NCO1IE
—
CWG3IE
bit 7
R/W-0/0
CWG2IE
R/W-0/0
CWG1IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
SCANIE: Scanner Interrupt Enable bit
1 = Enables the scanner interrupt
0 = Disables the scanner interrupt
bit 6
CRCIE: CRC Interrupt Enable bit
1 = Enables the CRC interrupt
0 = Disables the CRC interrupt
bit 5
NVMIE: NVM Interrupt Enable bit
1 = NVM task complete interrupt enabled
0 = NVM interrupt not enabled
bit 4
NCO1IE: NCO Interrupt Enable bit
1 = NCO rollover interrupt enabled
0 = NCO rollover interrupt disabled
bit 3
Unimplemented: Read as ‘0’.
bit 2
CWG3IE: Complementary Waveform Generator (CWG) 3 Interrupt Enable bit
1 = CWG3 interrupt enabled
0 = CWG3 interrupt disabled
bit 1
CWG2IE: Complementary Waveform Generator (CWG) 2 Interrupt Enable bit
1 = CWG2 interrupt is enabled
0 = CWG2 interrupt disabled
bit 0
CWG1IE: Complementary Waveform Generator (CWG) 2 Interrupt Enable bit
1 = CWG1 interrupt is enabled
0 = CWG1 interrupt disabled
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
DS40001824A-page 140
Preliminary
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