PIC16LF18854 Datasheet, PDF (451/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
30.3.4 TIMER2 TIMER RESOURCE
This device has a newer version of the TMR2 module
that has many new modes, which allow for greater
customization and control of the PWM signals than on
older parts. Refer to Section 29.5, Operation Examples
for examples of PWM signal generation using the
different modes of Timer2. The CCP operation requires
that the timer used as the PWM time base has the
FOSC/4 clock source selected
30.3.5 PWM PERIOD
The PWM period is specified by the PR2/4/6 register of
Timer2/4/6. The PWM period can be calculated using
the formula of Equation 30-1.
EQUATION 30-1: PWM PERIOD
PWM Period = PR2 + 1  4  TOSC 
(TMR2 Prescale Value)
Note 1: TOSC = 1/FOSC
When TMR2/4/6 is equal to PR2, the following three
events occur on the next increment cycle:
• TMR2/4/6 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is transferred from the
CCPRxL/H register pair into a 10-bit buffer.
Note:
The Timer postscaler (see Section 29.4
“Timer2 Interrupt”) is not used in the
determination of the PWM frequency.
30.3.6 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the CCPRxH:CCPRxL register pair. The
alignment of the 10-bit value is determined by the
CCPRxFMT bit of the CCPxCON register (see
Figure 30-5). The CCPRxH:CCPRxL register pair can
be written to at any time; however the duty cycle value
is not latched into the 10-bit buffer until after a match
between PR2 and TMR2.
Equation 30-2 is used to calculate the PWM pulse
width.
Equation 30-3 is used to calculate the PWM duty cycle
ratio.
FIGURE 30-5:
PWM 10-BIT ALIGNMENT
CCPRxH
76543210
CCPRxL
76543210
Rev. 10-000 160A
12/9/201 3
FMT = 0
FMT = 1
CCPRxH
76543210
CCPRxL
76543210
10-bit Duty Cycle
9876543210
EQUATION 30-2: PULSE WIDTH
Pulse Width = CCPRxH:CCPRxL register pair 
TOSC  (TMR2 Prescale Value)
EQUATION 30-3: DUTY CYCLE RATIO
Duty Cycle Ratio = ^---C----C----P----R---x---H----:--4C---_-C--P--P--R--R--₂--x--L+-----r-1--e-_-g---i--s--t--e---r---p---a---i--r---^
CCPRxH:CCPRxL register pair are used to double
buffer the PWM duty cycle. This double buffering is
essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the
CCPRxH:CCPRxL register pair, then the CCPx pin is
cleared (see Figure 30-4).
30.3.7 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 30-4.
EQUATION 30-4: PWM RESOLUTION
Resolution = ^{l--o---g----}--4---l-^_{o--P-g---R-}--2-²---_--+-----1----^--^ bits
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 451