PIC16LF18854 Datasheet, PDF (129/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 7-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt
GIE
Interrupt Sampled
during Q1
PC
PC-1
PC
Execute 1 Cycle Instruction at PC
PC+1
Inst(PC)
NOP
0004h
NOP
0005h
Inst(0004h)
Interrupt
GIE
PC
PC-1
PC
Execute 2 Cycle Instruction at PC
PC+1/FSR
ADDR
Inst(PC)
New PC/
PC+1
NOP
0004h
NOP
0005h
Inst(0004h)
Interrupt
GIE
PC
PC-1
PC
FSR ADDR
Execute 3 Cycle Instruction at PC
INST(PC)
PC+1
NOP
Interrupt
GIE
PC
PC-1
PC
FSR ADDR
Execute 3 Cycle Instruction at PC
INST(PC)
PC+1
NOP
PC+2
NOP
0004h
NOP
0005h
Inst(0004h) Inst(0005h)
PC+2
NOP
NOP
0004h
NOP
0005h
Inst(0004h)
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 129