PIC16LF18854 Datasheet, PDF (432/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
29.5.6
EDGE-TRIGGERED ONE-SHOT
MODE
The Edge-Triggered One-Shot modes start the timer
on an edge from the external signal input, after the ON
bit is set, and clear the ON bit when the timer matches
the PRx period value. The following edges will start the
timer:
• Rising edge (MODE<4:0> = 01001)
• Falling edge (MODE<4:0> = 01010)
• Rising or Falling edge (MODE<4:0> = 01011)
If the timer is halted by clearing the ON bit then another
TMRx_ers edge is required after the ON bit is set to
resume counting. Figure 29-9 illustrates operation in
the rising edge One-Shot mode.
When Edge-Triggered One-Shot mode is used in con-
junction with the CCP then the edge-trigger will activate
the PWM drive and the PWM drive will deactivate when
the timer matches the CCPRx pulse width value and
stay deactivated when the timer halts at the PRx period
count match.
FIGURE 29-9:
EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)
Rev. 10-000200B
5/30/2014
MODE
TMRx_clk
PRx
Instruction⁽¹⁾
BSF
ON
TMRx_ers
TMRx
0
TMRx_out
TMRx_postscaled
12345
0b01001
5
BSF
0
BCF
1
2
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
29.5.7
EDGE-TRIGGERED HARDWARE
LIMIT ONE-SHOT MODE
In Edge-Triggered Hardware Limit One-Shot modes
the timer starts on the first external signal edge after
the ON bit is set and resets on all subsequent edges.
Only the first edge after the ON bit is set is needed to
start the timer. The counter will resume counting
automatically two clocks after all subsequent external
Reset edges. Edge triggers are as follows:
• Rising edge start and Reset
(MODE<4:0> = 01100)
• Falling edge start and Reset
(MODE<4:0> = 01101)
The timer resets and clears the ON bit when the timer
value matches the PRx period value. External signal
edges will have no effect until after software sets the
ON bit. Figure 29-10 illustrates the rising edge hard-
ware limit one-shot operation.
When this mode is used in conjunction with the CCP
then the first starting edge trigger, and all subsequent
Reset edges, will activate the PWM drive. The PWM
drive will deactivate when the timer matches the
CCPRx pulse-width value and stay deactivated until
the timer halts at the PRx period match unless an exter-
nal signal edge resets the timer before the match
occurs.
DS40001824A-page 432
Preliminary
 2016 Microchip Technology Inc.