PIC16LF18854 Datasheet, PDF (445/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 29-3: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
EN
—
OUT
FMT
MODE<3:0>
CCP2CON
EN
—
OUT
FMT
MODE<3:0>
CCPTMRS0
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
CCPTMRS1
—
—
P7TSEL<1:0>
P6TSEL<1:0>
C5TSEL<1:0>
INTCON
GIE
PEIE
—
—
—
—
—
INTEDG
PIE1
OSFIE
CSWIE
—
—
—
—
ADTIE
ADIE
PIR1
OSFIF
CSWIF
—
—
—
—
ADTIF
ADIF
PR2
Timer2 Module Period Register
TMR2
Holding Register for the 8-bit TMR2 Register
T2CON
ON
CKPS<2:0>
OUTPS<3:0>
T2CLKCON
—
—
—
—
CS<3:0>
T2RST
—
—
—
RSEL<4:0>
T2HLT
PSYNC
CKPOL CKSYNC
—
MODE<3:0>
PR4
Timer4 Module Period Register
TMR4
Holding Register for the 8-bit TMR4 Register
T4CON
ON
CKPS<2:0>
OUTPS<3:0>
T4CLKCON
—
—
—
—
—
CS<3:0>
T4RST
—
—
—
RSEL<4:0>
T4HLT
PSYNC
CKPOL CKSYNC
—
MODE<3:0>
PR6
Timer6 Module Period Register
TMR6
Holding Register for the 8-bit TMR6 Register
T6CON
ON
CKPS<2:0>
OUTPS<3:0>
T6CLKCON
—
—
—
—
—
CS<2:0>
T6RST
—
—
—
RSEL<4:0>
T6HLT
PSYNC
CKPOL CKSYNC
—
MODE<3:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.
Register
on Page
453
453
456
456
132
134
143
424*
424*
442
441
444
443
424*
424*
442
441
444
443
424*
424*
442
441
444
443
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 445