PIC16LF18854 Datasheet, PDF (138/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-7: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
CLC4IE
CLC3IE
CLC2IE
CLC1IE
—
TMR5GIE
bit 7
R/W-0/0
TMR3GIE
R/W-0/0
TMR1GIE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
CLC4IE: CLC4 Interrupt Enable bit
1 = CLC4 interrupt enabled
0 = CLC4 interrupt disabled
bit 6
CLC3IE: CLC3 Interrupt Enable bit
1 = CLC3 interrupt enabled
0 = CLC3 interrupt disabled
bit 5
CLC2IE: CLC2 Interrupt Enable bit
1 = CLC2 interrupt enabled
0 = CLC2 interrupt disabled
bit 4
CLC1IE: CLC1 Interrupt Enable bit
1 = CLC1 interrupt enabled
0 = CLC1 interrupt disabled
bit 3
Unimplemented: Read as ‘0’
bit 2
TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enables the Timer5 gate acquisition interrupt
0 = Disables the Timer5 gate acquisition interrupt
bit 1
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enables the Timer3 gate acquisition interrupt
0 = Disables the Timer3 gate acquisition interrupt
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
DS40001824A-page 138
Preliminary
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