PIC16LF18854 Datasheet, PDF (130/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 7-3:
INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT ⁽³⁾
(4)
INT pin
INTF
(1)
(1)
(5)
Interrupt Latency ⁽²⁾
GIE
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst (PC)
PC + 1
Inst (PC + 1)
PC + 1
—
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
Executed
Inst (PC – 1)
Inst (PC)
Forced NOP
Forced NOP
Inst (0004h)
Note 1:
2:
3:
4:
5:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT not available in all oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 37.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
DS40001824A-page 130
Preliminary
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