PIC16LF18854 Datasheet, PDF (583/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
34.0 REFERENCE CLOCK OUTPUT
MODULE
The Reference Clock Output module provides the
ability to send a clock signal to the clock reference
output pin (CLKR). The Reference Clock Output can
also be used as a signal for other peripherals, such as
the Data Signal Modulator (DSM).
The Reference Clock Output module has the following
features:
• Selectable input clock
• Programmable clock divider
• Selectable duty cycle
34.1 CLOCK SOURCE
The Reference Clock Output module has a selectable
clock source. The CLKRCLK register (Register 34-2)
controls which input is used.
34.1.1 CLOCK SYNCHRONIZATION
Once the reference clock enable (CLKREN) is set, the
module is ensured to be glitch-free at start-up.
When the Reference Clock Output is disabled, the
output signal will be disabled immediately.
Clock dividers and clock duty cycles can be changed
while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.
34.2 PROGRAMMABLE CLOCK
DIVIDER
The module takes the system clock input and divides it
based on the value of the CLKRDIV<2:0> bits of the
CLKRCON register (Register 34-1).
The following configurations can be made based on the
CLKRDIV<2:0> bits:
• Base FOSC value
• FOSC divided by 2
• FOSC divided by 4
• FOSC divided by 8
• FOSC divided by 16
• FOSC divided by 32
• FOSC divided by 64
• FOSC divided by 128
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the CLKRDIV<2:0> bits should
only be changed when the module is disabled
(CLKREN = 0).
34.3 SELECTABLE DUTY CYCLE
The CLKRDC<1:0> bits of the CLKRCON register can
be used to modify the duty cycle of the output clock. A
duty cycle of 25%, 50%, or 75% can be selected for all
clock rates, with the exception of the undivided base
FOSC value.
The duty cycle can be changed while the module is
enabled; however, in order to prevent glitches on the
output, the CLKRDC<1:0> bits should only be changed
when the module is disabled (CLKREN = 0).
Note:
The CLKRDC1 bit is reset to ‘1’. This
makes the default duty cycle 50% and not
0%.
34.4 OPERATION IN SLEEP MODE
The Reference Clock Output module clock is based on
the system clock. When the device goes to Sleep, the
module outputs will remain in their current state. This
will have a direct effect on peripherals using the
Reference Clock Output as an input signal.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 583