PIC16LF18854 Datasheet, PDF (574/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
33.6 Register Definitions: EUSART Control
REGISTER 33-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
CSRC
bit 7
R/W-0/0
TX9
R/W-0/0
TXEN⁽¹⁾
R/W-0/0
SYNC
R/W-0/0
SENDB
R/W-0/0
BRGH
R-1/1
TRMT
R/W-0/0
TX9D
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit⁽¹⁾
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send SYNCH BREAK on next transmission – start bit, followed by 12 ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = SYNCH BREAK transmission disabled or completed
Synchronous mode:
Unused in this mode – value ignored
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode – value ignored
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS40001824A-page 574
Preliminary
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