PIC16LF18854 Datasheet, PDF (174/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
10.4.5 NVMREG WRITE TO PFM
Program memory is programmed using the following
steps:
1. Load the address of the row to be programmed
into NVMADRH:NVMADRL.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-4 (row writes to program memory with 32
write latches) for more details.
The write latches are aligned to the Flash row address
boundary defined by the upper ten bits of
NVMADRH:NVMADRL, (NVMADRH<6:0>:NVMADRL<7:5>)
with the lower five bits of NVMADRL, (NVMADRL<4:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the
NVMDATH:NVMDATL using the unlock sequence with
LWLO = 1. When the last word to be loaded into the
write latch is ready, the LWLO bit is cleared and the
unlock sequence executed. This initiates the
programming operation, writing all the latches into
Flash program memory.
Note:
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
1. Set the WREN bit of the NVMCON1 register.
2. Clear the NVMREGS bit of the NVMCON1
register.
3. Set the LWLO bit of the NVMCON1 register.
When the LWLO bit of the NVMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the NVMADRH:NVMADRL register pair
with the address of the location to be written.
5. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
6. Execute the unlock sequence (Section
10.4.2 “NVM Unlock Sequence”). The write
latch is now loaded.
7. Increment the NVMADRH:NVMADRL register
pair to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the NVMCON1 register.
When the LWLO bit of the NVMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
11. Execute the unlock sequence (Section
10.4.2 “NVM Unlock Sequence”). The entire
program memory latch content is now written to
Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-4. The initial address is loaded into the
NVMADRH:NVMADRL register pair; the data is loaded
using indirect addressing.
DS40001824A-page 174
Preliminary
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