PIC16LF18854 Datasheet, PDF (244/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
13.1 PPS Inputs
Each peripheral has a PPS register with which the
inputs to the peripheral are selected. Inputs include the
device pins.
Although every peripheral has its own PPS input
selection register, the selections are identical for every
peripheral as shown in Register 13-1..
Note:
The notation “xxx” in the register name is
a place holder for the peripheral identifier.
For example, CLC1PPS.
13.2 PPS Outputs
Each I/O pin has a PPS register with which the pin
output source is selected. With few exceptions, the port
TRIS control associated with that pin retains control
over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
override the TRIS control as needed. These
peripherals include:
• EUSART (synchronous operation)
• MSSP (I²C)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 13-2.
Note:
The notation “Rxy” is a place holder for the
pin port and bit identifiers. For example, x
and y for PORTA bit 0 would be A and 0,
respectively, resulting in the pin PPS
output selection register RA0PPS.
FIGURE 13-1:
SIMPLIFIED PPS BLOCK DIAGRAM
PPS Outputs
PPS Inputs
RA0PPS
abcPPS
RA0
RA0
Peripheral abc
RxyPPS
Rxy
RE2⁽¹⁾
xyzPPS
Peripheral xyz
R E2PPS⁽¹⁾
RE2⁽¹⁾
Note 1: RD<7:0> and RE<2:0> are only implemented on the 40/44-pin devices.
RE3 is PPS input capable only (when MLCR is disabled).
DS40001824A-page 244
Preliminary
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