PIC16LF18854 Datasheet, PDF (198/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
12.0 I/O PORTS
TABLE 12-1: PORT AVAILABILITY PER
DEVICE
Device
PIC16(L)F18856
PIC16(L)F18876
● ●●
●
● ● ●●●
Each port has ten standard registers for its operation.
These registers are:
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
• TRISx registers (data direction)
• ANSELx registers (analog select)
• WPUx registers (weak pull-up)
• CCDPx registers (current control positive)
• CCDNx registers (current control negative)
• INLVLx (input level control)
• SLRCONx registers (slew rate)
• ODCONx registers (open-drain)
Most port pins share functions with device peripherals,
both analog and digital. In general, when a peripheral
is enabled on a port pin, that pin cannot be used as a
general purpose output; however, the pin can still be
read.
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.
FIGURE 12-1:
GENERIC I/O PORT
OPERATION
Read LATx _TRISx
Write LATx
Write PORTx
D
Q
CK
Data Register
Data Bus
Read PORTx
To digital peripherals
To analog peripherals
ANSELx
VDD
I/O pin
VSS
12.1 Current-Controlled Mode
Current-Controlled mode allows output currents to be
regulated for both high-side and low-side drivers. All
source and sink drivers for each port pin will operate at
the specified current, when enabled individually by the
Current-Controlled Enable registers.
Note:
Current-Controlled mode is available
regardless of which peripheral drives the
output.
The Current-Controlled Configuration (CCDCON) reg-
ister enables the Current-Controlled mode for all ports
and sets the current levels.
Note:
Setting CCDEN = 1 increases the device
VDDIO current requirement by a fixed
amount regardless of how many
CCDPx[n] or CCDNx[n] bits are set.
The Current-Controlled Enable registers enable each
individual port pin’s positive-going (CCDPx) or
negative-going (CCDNx) output driver.
DS40001824A-page 198
Preliminary
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