PIC16LF18854 Datasheet, PDF (464/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
31.2.2 SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<3:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of the
SSPxCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPxCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial port
pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the TRISx
register) appropriately programmed as follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
The MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb first.
The SSPxBUF holds the data that was written to the
SSPxSR until the received data is ready. Once the eight
bits of data have been received, that byte is moved to the
SSPxBUF register. Then, the Buffer Full Detect bit, BF of
the SSPxSTAT register, and the interrupt flag bit, SSPxIF,
are set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPxBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL of
the SSPxCON1 register, will be set. User software must
clear the WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF of the SSPxSTAT register, indicates
when SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various Status conditions.
FIGURE 31-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010 _SDO
Serial Input Buffer
(SSPxBUF)
SPI Slave SSPM<3:0> = 010x
SDI
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
MSb
LSb
SDI
SCK
General I/O
Processor 1
Serial Clock
Slave Select
(optional)
SDO
SCK
Shift Register
(SSPxSR)
MSb
LSb
SS
Processor 2
DS40001824A-page 464
Preliminary
 2016 Microchip Technology Inc.