PIC16LF18854 Datasheet, PDF (233/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
12.14 PORTE Registers
(PIC16(L)F18876)
12.14.1 DATA REGISTER
PORTE is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE
(Register 12-46). Setting a TRISE bit (= 1) will make
the corresponding PORTE pin an input (i.e., disable the
output driver). Clearing a TRISE bit (= 0) will make the
corresponding PORTE pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 12.4.9 shows how to
initialize PORTE.
Reading the PORTE register (Register 12-45) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is
modified and then written to the PORT data latch
(LATE).
The PORT data latch LATE (Register 12-47) holds the
output port data, and contains the latest value of a
LATE or PORTE write.
12.14.2 DIRECTION CONTROL
The TRISE register (Register 12-46) controls the
PORTE pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISE register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
12.14.3 INPUT THRESHOLD CONTROL
The INLVLE register (Register 12-52) controls the input
voltage threshold for each of the available PORTE
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTE register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Table 37-4 for more information on
threshold levels.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
12.14.4 OPEN-DRAIN CONTROL
The ODCONE register (Register 12-50) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONE bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONE bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
Note:
It is not necessary to set open-drain
control when using the pin for I²C; the I²C
module controls the pin and makes the pin
open-drain.
12.14.5 SLEW RATE CONTROL
The SLRCONE register (Register 12-51) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONE bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONE bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
12.14.6 ANALOG CONTROL
The ANSELE register (Register 12-48) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELE bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELE set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
Note:
The ANSELC bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
12.14.7 WEAK PULL-UP CONTROL
The WPUE register (Register 12-49) controls the
individual weak pull-ups for each port pin.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 233