PIC16LF18854 Datasheet, PDF (414/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
28.7 Timer1 Interrupts
The timer register pair (TMR1H:TMR1L) increments to
FFFFh and rolls over to 0000h. When the timer rolls
over, the respective timer interrupt flag bit of the PIR5
register is set. To enable the interrupt on rollover, you
must set these bits:
• ON bit of the T1CON register
• TMR1IE bit of the PIE4 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
To avoid immediate interrupt vectoring,
the TMR1H:TMR1L register pair should
be preloaded with a value that is not immi-
nently about to rollover, and the TMR1IF
flag should be cleared prior to enabling
the timer interrupts.
28.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• ON bit of the T1CON register must be set
• TMR1IE bit of the PIE4 register must be set
• PEIE bit of the INTCON register must be set
• SYNC bit of the T1CON register must be set
• CLK bits of the T1CLK register must be
configured
• The timer clock source must be enabled and
continue operation during sleep. When the SOSC
is used for this purpose, the SOSCEN bit of the
OSCEN register must be set.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Secondary oscillator will continue to operate in Sleep
regardless of the SYNC bit setting.
28.9 CCP Capture/Compare Time Base
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPRxH:CCPRxL
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPRxH:CCPRxL register pair matches the value in
the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.
The Timer1 to CCP1/2/3/4/5 mapping is not fixed, and
can be assigned on an individual CCP module basis.
All of the CCP modules may be configured to share a
single Timer1 (or Timer3, or Timer5) resource, or
different CCP modules may be configured to use
different Timer1 resources. This timer to CCP mapping
selection is made in the CCPTMRS0 and CCPTMRS1
registers.
For more information, see Section 30.0
“Capture/Compare/PWM Modules”.
28.10 CCP Auto-Conversion Trigger
When any of the CCP’s are configured to trigger an
auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
does not cause a timer interrupt. The CCP module may
still be configured to generate a CCP interrupt.
In this mode of operation, the CCPRxH:CCPRxL
register pair becomes the period register for Timer1.
The timer should be synchronized and FOSC/4 should
be selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
the timer can cause an Auto-conversion Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with an Auto-conversion Trigger from the CCP, the
write will take precedence.
For more information, see Section 30.2.4 “Compare
During Sleep”.
DS40001824A-page 414
Preliminary
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