PIC16LF18854 Datasheet, PDF (290/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
20.0 COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG) pro-
duces half-bridge, full-bridge, and steering of PWM
waveforms. It is backwards compatible with previous
ECCP functions.
The CWG has the following features:
• Six operating modes:
- Synchronous Steering mode
- Asynchronous Steering mode
- Full-Bridge mode, Forward
- Full-Bridge mode, Reverse
- Half-Bridge mode
- Push-Pull mode
• Output polarity control
• Output steering
- Synchronized to rising event
- Immediate effect
• Independent 6-bit rising and falling event dead-
band timers
- Clocked dead band
- Independent rising and falling dead-band
enables
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
The CWG modules available are shown in Table 20-1.
TABLE 20-1: AVAILABLE CWG MODULES
Device
CWG1 CWG2 CWG2
PIC16(L)F18856/76
●
●
●
20.1 Fundamental Operation
The CWG module can operate in six different modes,
as specified by MODE of the CWGxCON0 register:
• Half-Bridge mode (Figure 20-9)
• Push-Pull mode (Figure 20-2)
- Full-Bridge mode, Forward (Figure 20-3)
- Full-Bridge mode, Reverse (Figure 20-3)
• Steering mode (Figure 20-10)
• Synchronous Steering mode (Figure 20-11)
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. Thus, all
output modes support auto-shutdown, which is covered
in 20.10 “Auto-Shutdown”.
20.1.1 HALF-BRIDGE MODE
In Half-Bridge mode, two output signals are generated
as true and inverted versions of the input as illustrated
in Figure 20-9. A non-overlap (dead-band) time is
inserted between the two outputs to prevent shoot
through current in various power supply applications.
Dead-band control is described in Section
20.5 “Dead-Band Control”.
The unused outputs CWGxC and CWGxD drive similar
signals, with polarity independently controlled by the
POLC and POLD bits of the CWGxCON1 register,
respectively.
DS40001824A-page 290
Preliminary
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