PIC16LF18854 Datasheet, PDF (232/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 12-44: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER
U-0
U-0
U-0
U-0
R/W-1/1
U-0
U-0
—
—
—
—
INLVLE3
—
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
INLVLE3: PORTE Input Level Select bits
For RE3 pin,
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change
Unimplemented: Read as ‘0’
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PORTE
WPUE
INLVLE
Legend:
—
—
—
—
RE3
—
—
—
231
—
—
—
—
WPUE3
—
—
—
231
—
—
—
—
INLVLE3
—
—
—
232
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
TABLE 12-7: SUMMARY OF CONFIGURATION WORD WITH PORTE
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1
13:8
CONFIG2
7:0
—
—
BOREN<1:0>
DEBUG ^{STVREN PPS1WAY ZCDDIS BORV}
LPBOREN —
—
—
PWRTE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.
Bit 8/0
—
MCLRE
Register
on Page
92
DS40001824A-page 232
Preliminary
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