PIC16LF18854 Datasheet, PDF (617/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 37-7:
Cycle
FOSC
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
CLKOUT AND I/O TIMING
Write
Q4
Fetch
Q1
IO1
IO8
Read
Q2
IO10
IO4
IO5
Old Value
IO3
IO7, IO8
Execute
Q3
IO2
IO7
New Value
TABLE 37-10: I/O AND CLKOUT TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
IO1*
T_CLKOUTH CLKOUT rising edge delay (rising edge
—
Fosc (Q1 cycle) to falling edge CLKOUT
IO2*
T_CLKOUTL CLKOUT falling edge delay (rising edge
—
Fosc (Q3 cycle) to rising edge CLKOUT
IO3*
T_{IO_VALID} Port output valid time (rising edge Fosc
—
(Q1 cycle) to port valid)
IO4*
T_{IO_SETUP} Port input setup time (Setup time before
20
rising edge Fosc – Q2 cycle)
IO5*
T_{IO_HOLD} Port input hold time (Hold time after rising
50
edge Fosc – Q2 cycle)
IO6*
T_{IOR_SLREN} Port I/O rise time, slew rate enabled
—
IO7*
T_{IOR_SLRDIS} Port I/O rise time, slew rate disabled
—
IO8*
T_{IOF_SLREN} Port I/O fall time, slew rate enabled
—
IO9*
T_{IOF_SLRDIS} Port I/O fall time, slew rate disabled
—
IO10* T_INT
INT pin high or low time to trigger an
25
interrupt
IO11* T_IOC
Interrupt-on-Change minimum high or low
25
time to trigger interrupt
*These parameters are characterized but not tested.
Typ† Max. Units Conditions
—
70
ns
—
72
ns
50
70
ns
—
—
ns
—
—
ns
25
—
ns VDD = 3.0V
5
—
ns VDD = 3.0V
25
—
ns VDD = 3.0V
5
—
ns VDD = 3.0V
—
—
ns
—
—
ns
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 617