PIC16LF18854 Datasheet, PDF (410/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
28.0 TIMER1/3/5 MODULE WITH
GATE CONTROL
The Timer1/3/5 modules are 16-bit timer/counters with
the following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle mode
FIGURE 28-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1GPPS
PPS
00
T0_overflow
01
C1OUT_sync
10
C2OUT_sync
11
T1GPOL
TMR1ON
T1GTM
D
Q
CK
Q
R
• Gate Single-Pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 28-1 is a block diagram of the Timer1 module.
This device has three instances of Timer1 type mod-
ules. They include:
• Timer1
• Timer3
• Timer5
All references to Timer1 and Timer1 Gate apply equally
to Timer3 and Timer5.
T1GSPM
Rev. 10-000018H
7/28/2015
1
0
Single Pulse
D
Q
T1GVAL
1
Acq. Control
0
Q1
T1GGO/DONE
Interrupt
det
set bit
TMR1GIF
set flag bit
TMR1IF
T1_overflow
TMR1⁽²⁾
TMR1H TMR1L
T1CLK
TMR1GE
EN
Q
D
TMR1ON
Synchronized Clock Input
0
1
T1SYNC
TMR1CS<1:0>
T1CKI
(1)
PPS
T1CKIPPS
LFINTOSC
Fosc
Internal Clock
Fosc/4
Internal Clock
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
11
10
Prescaler
01
1,2,4,8
Synchronize⁽³⁾
det
00
2
Fosc/2
T1CKPS<1:0> _Internal
Sleep
Clock
Input
DS40001824A-page 410
Preliminary
 2016 Microchip Technology Inc.