PIC16LF18854 Datasheet, PDF (285/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
19.1.1 PWM CLOCK SELECTION
The PIC16(L)F18855/75 allows each individual CCP
and PWM module to select the timer source that con-
trols the module. Each module has an independent
selection.
As there are up to three 8-bit timers with auto-reload
(Timer2/4/6), PWM mode on the CCP and PWM mod-
ules can use any of these timers.
The CCPTMRS0 and CCPTMRS1 register are used to
select which timer is used.
19.1.2
USING THE TMR2/4/6 WITH THE
PWM MODULE
This device has a newer version of the TMR2 module
that has many new modes, which allow for greater cus-
tomization and control of the PWM signals than on
older parts. Refer to Section 29.5, Operation Examples
for examples of PWM signal generation using the dif-
ferent modes of Timer2. PWM operation requires that
the timer used as the PWM time base has the FOSC/4
clock source selected.
19.1.3 PWM PERIOD
Referring to Figure 19-1, the PWM output has a period
and a pulse width. The frequency of the PWM is the
inverse of the period (1/period).
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 19-1: PWM PERIOD
݀݋݅ݎ݁ܲܯܹܲൌ  ሾሺܴܲʹሻ  ൅ ͳሿ  ή Ͷ ή ܥܱܵܶ
ή  ሺܶ݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯሻ
Note 1: TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The PWMx pin is set (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM pulse width is latched from PWMxDC.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
19.1.4 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDC register. The PWMxDCH
contains the eight MSbs and the PWMxDCL<7:6> bits
contain the two LSbs.
The PWMDC register is double-buffered and can be
updated at any time. This double buffering is essential
for glitch-free PWM operation. New values take effect
when TMR2 = PR2. Note that PWMDC is left-justified.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two
bits of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
Equation 19-2 is used to calculate the PWM pulse
width.
Equation 19-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 19-2: PULSE WIDTH
Pulse Widthൌሺܹܲܥܦݔܯሻ  ή ܥܱܵܶή
ሺܶ݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯሻ
EQUATION 19-3: DUTY CYCLE RATIO
ሺܹܲܥܦݔܯሻ
݋݅ݐܴ݈ܽ݁ܿݕܥݕݐݑܦൌ  _{Ͷሺܴܲʹ ൅ ͳሻ}
19.1.5 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit
resolution will result in 1024 discrete duty cycles,
whereas an 8-bit resolution will result in 256 discrete
duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 19-4.
EQUATION 19-4: PWM RESOLUTION
Resolution = ^{l--o---g----}--4--l--^_o--^P-g---^R-_--2-2--_---+-----1---^--^- bits
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
19.1.6 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 285