PIC16LF18854 Datasheet, PDF (108/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
5.13 Register Definitions: Power Control
REGISTER 5-2: PCON0: POWER CONTROL REGISTER 0
R/W/HS-0/q R/W/HS-0/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q
STKOVF
STKUNF
WDTWV
RWDT
RMCLR
bit 7
R/W/HC-1/q
RI
R/W/HC-q/u R/W/HC-q/u
POR
BOR
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
-m/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6
STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5
WDTWV: WDT Window Violation Flag bit
1 = A WDT Window Violation Reset has not occurred or set by firmware
0 = A WDT Window Violation Reset has occurred (a CLRWDT instruction was executed either without
arming the window or outside the window (cleared by hardware)
bit 4
RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2
RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BORCON SBOREN
—
—
—
—
—
—
PCON0
STKOVF STKUNF WDTWV RWDT RMCLR
RI
POR
STATUS
—
—
—
TO
PD
Z
DC
WDTCON0
—
—
WDTPS<4:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
Bit 0
Register
on Page
BORRDY 103
BOR
108
C
38
SWDTEN 164
DS40001824A-page 108
Preliminary
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