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PIC16LF18854 Datasheet, PDF (594/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture | |||
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PIC16(L)F18856/76
BCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Clear f
[ label ] BCF f,b
0 ï£ f ï£ 127
0ï£bï£7
0 ï® (f<b>)
None
Bit âbâ in register âfâ is cleared.
BRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Relative Branch
[ label ] BRA label
[ label ] BRA $+k
-256 ï£ label - PC + 1 ï£ 255
-256 ï£ k ï£ 255
(PC) + 1 + k ï® PC
None
Add the signed 9-bit literal âkâ to the
PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + k. This instruction is a
2-cycle instruction. This branch has a
limited range.
BRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Relative Branch with W
[ label ] BRW
None
(PC) + (W) ï® PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.
BSF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Set f
[ label ] BSF f,b
0 ï£ f ï£ 127
0ï£bï£7
1 ï® (f<b>)
None
Bit âbâ in register âfâ is set.
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Clear
[ label ] BTFSC f,b
0 ï£ f ï£ 127
0ï£bï£7
skip if (f<b>) = 0
None
If bit âbâ in register âfâ is â1â, the next
instruction is executed.
If bit âbâ, in register âfâ, is â0â, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 ï£ f ï£ 127
0ï£b<7
skip if (f<b>) = 1
None
If bit âbâ in register âfâ is â0â, the next
instruction is executed.
If bit âbâ is â1â, then the next instruction
is discarded and a NOP is executed
instead, making this a 2-cycle
instruction.
DS40001824A-page 594
Preliminary
ï£ 2016 Microchip Technology Inc.
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