|
PIC16LF18854 Datasheet, PDF (292/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture | |||
|
◁ |
PIC16(L)F18856/76
20.1.2 PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 20-2. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWGxA.
The unused outputs CWGxC and CWGxD drive copies
of CWGxA and CWGxB, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWGxCON1 register, respectively.
20.1.3 FULL-BRIDGE MODES
In Forward and Reverse Full-Bridge modes, three out-
puts drive static values while the fourth is modulated by
the input data signal. In Forward Full-Bridge mode,
CWGxA is driven to its active state, CWGxB and
CWGxC are driven to their inactive state, and CWGxD
is modulated by the input signal. In Reverse Full-Bridge
mode, CWGxC is driven to its active state, CWGxA and
CWGxD are driven to their inactive states, and CWGxB
is modulated by the input signal. In Full-Bridge mode,
the dead-band period is used when there is a switch
from forward to reverse or vice-versa. This dead-band
control is described in Section 20.5 âDead-Band Con-
trolâ, with additional details in Section 20.6 âRising
Edge and Reverse Dead Bandâ and Section
20.7 âFalling Edge and Forward Dead Bandâ.
The mode selection may be toggled between forward
and reverse toggling the MODE<0> bit of the
CWGxCON0 while keeping MODE<2:1> static, without
disabling the CWG module.
DS40001824A-page 292
Preliminary
ï£ 2016 Microchip Technology Inc.
|
▷ |