PIC16LF18854 Datasheet, PDF (42/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-5: PIC16F18856/76 MEMORY MAP BANK 8-15
400h
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
46Fh
470h
47Fh
BANK 8
Core Registers
(Table 3-2)
SCANLADRL
SCANLADRH
SCANHADRL
SCANHADRH
SCANCON0
SCANTRIG
—
—
—
—
CRCDATL
CRCDATH
CRCACCL
CRCACCH
CRCSHIFTL
CRCSHIFTH
CRCXORL
CRCXORH
CRCCON0
CRCCON1
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
480h
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
4EFh
4F0h
4FFh
BANK 9
Core Registers
(Table 3-2)
SMT1TMRL
SMT1TMRH
SMT1TMRU
SMT1CPRL
SMT1CPRH
SMT1CPRU
SMT1CPWL
SMT1CPWH
SMT1CPWU
SMT1PRL
SMT1PRH
SMT1PRU
SMT1CON0
SMT1CON1
SMT1STAT
SMT1CLK
SMT1SIG
SMT1WIN
—
—
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
500h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
56Fh
570h
57Fh
BANK 10
Core Registers
(Table 3-2)
SMT2TMRL
SMT2TMRH
SMT2TMRU
SMT2CPRL
SMT2CPRH
SMT2CPRU
SMT2CPWL
SMT2CPWH
SMT2CPWU
SMT2PRL
SMT2PRH
SMT2PRU
SMT2CON0
SMT2CON1
SMT2STAT
SMT2CLK
SMT2SIG
SMT2WIN
—
—
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
580h
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
5FFh
BANK 11
Core Registers
(Table 3-2)
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
NCO1INCU
NCO1CON
NCO1CLK
—
—
—
—
—
—
—
—
—
—
—
—
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
600h
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
66Fh
670h
67Fh
BANK 12
Core Registers
(Table 3-2)
CWG1CLKCON
CWG1ISM
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1AS0
CWG1AS1
CWG1STR
—
CWG2CLKCON
CWG2ISM
CWG2DBR
CWG2DBF
CWG2CON0
CWG2CON1
CWG2AS0
CWG2AS1
CWG2STR
—
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
680h
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
6FFh
BANK 13
Core Registers
(Table 3-2)
CWG3CLKCON
CWG3ISM
CWG3DBR
CWG3DBF
CWG3CON0
CWG3CON1
CWG3AS0
CWG3AS1
CWG3STR
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
700h
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
77Fh
BANK 14
Core Registers
(Table 3-2)
PIR0
PIR1
PIR2
PIR3
PIR4
PIR5
PIR6
PIR7
PIR8
—
PIE0
PIE1
PIE2
PIE3
PIE4
PIE5
PIE6
PIE7
PIE8
—
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
780h
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
7FFh
BANK 15
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
—
—
—
—
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.