PIC16LF18854 Datasheet, PDF (43/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-6: PIC16F18856/76 MEMORY MAP BANK 16-23
BANK 16
BANK 17
BANK 18
BANK 19
800h
80Bh
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh
820h
86Fh
870h
87Fh
Core Registers
(Table 3-2 )
WDTCON0
WDTCON1
WDTPSL
WDTPSH
WDTTMR
BORCON
VREGCON⁽¹⁾
PCON0
CCDCON
—
—
—
—
—
NVMADRL
NVMADRH
NVMDATL
NVMDATH
NVMCON1
NVMCON2
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
880h
88Bh
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
89Ch
89Dh
89Eh
89Fh
8A0h
8EFh
8F0h
8FFh
Core Registers
(Table 3-2)
CPUDOZE
OSCCON1
OSCCON2
OSCCON3
OSCSTAT
OSCEN
OSCTUNE
OSCFRQ
—
CLKRCON
CLKRCLK
MDCON0
MDCON1
MDSRC
MDCARL
MDCARH
—
—
—
—
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
900h
90Bh
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
91Fh
920h
96Fh
970h
97Fh
Core Registers
(Table 3-2)
FVRCON
—
DAC1CON0
DAC1CON1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ZCDCON
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
980h
98Bh
98Ch
98Dh
98Eh
98Fh
990h
991h
992h
993h
994h
995h
996h
997h
998h
999h
99Ah
99Bh
99Ch
99Dh
99Eh
99Fh
9A0h
9EFh
9F0h
9FFh
Core Registers
(Table 3-2)
—
—
—
CMOUT
CM1CON0
CM1CON1
CM1NSEL
CM1PSEL
CM2CON0
CM2CON1
CM2NSEL
CM2PSEL
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
A00h
A0Bh
A0Ch
A6Fh
A70h
A7Fh
BANK 20
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
A80h
A8Bh
A8Ch
AEFh
AF0h
AFFh
BANK 21
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
B00h
B0Bh
B0Ch
B6Fh
B70h
B7Fh
BANK 22
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
B80h
B8Bh
B8Ch
BEFh
BF0h
BFFh
BANK 23
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
Note 1: PIC16F18855/75 only.