PIC16LF18854 Datasheet, PDF (4/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1: PACKAGES
Packages
(S)PDIP SOIC
PIC16(L)F18856
PIC16(L)F18876



SSOP

QFN
(6x6)

UQFN
(4x4)

TQFP

QFN
(8x8)

UQFN
(5x5)

Note: Pin details are subject to change.
PIN DIAGRAMS
28-pin SPDIP, SOIC, SSOP
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC0
RC1
RC2
RC3
1
28
2
27
3
26
4
25
5
24
6
23
7 PIC16(L)F18856 ²²
8
21
9
20
10
19
11
18
12
17
13
16
14
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
Note 1:
2:
See Table 2 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins
to float may result in degraded electrical performance or non-functionality.
DS40001824A-page 4
Preliminary
 2016 Microchip Technology Inc.