PIC16LF18854 Datasheet, PDF (555/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
33.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 33-1 and Figure 33-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)
FIGURE 33-1:
EUSART TRANSMIT BLOCK DIAGRAM
SYNC
CSRC
CK pin
PPS
CKPPS
TXEN
1
0
Data Bus
TXxREG Register
MSb
8
LSb
(8)
•••
0
Transmit Shift Register (TSR)
TXIE
TXIF
Interrupt
RxyPPS⁽¹⁾
RX/DT pin
Pin Buffer
and Control
PPS
SYNC
Baud Rate Generator
BRG16
+1
SPxBRGH SPxBRGL
FOSC
÷n
n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
TX9
TX9D
Note 1: In Synchronous mode the DT output and RX input PPS
selections should enable the same pin.
TRMT
TX_out
SYNC
CSRC
0
PPS
1
TX/CK pin
RxyPPS
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 555