PIC16LF18854 Datasheet, PDF (544/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
32.8 Register Definitions: SMT Control
Long bit name prefixes for the Signal Measurement
Timer peripherals are shown in Section 1.1 “Register
and Bit naming conventions”.
TABLE 32-2: LONG BIT NAMES PREFIXES
FOR SMT PERIPHERALS
Peripheral
SMT1
SMT2
Bit Name Prefix
SMT1
SMT2
REGISTER 32-1: SMTxCON0: SMT CONTROL REGISTER 0
R/W-0/0
EN⁽¹⁾
bit 7
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
STP
WPOL
SPOL
R/W-0/0
CPOL
R/W-0/0
R/W-0/0
SMTxPS<1:0>
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
EN: SMT Enable bit⁽¹⁾
1 = SMT is enabled
0 = SMT is disabled; internal states are reset, clock requests are disabled
Unimplemented: Read as ‘0’
STP: SMT Counter Halt Enable bit
When SMTxTMR = SMTxPR:
1 = Counter remains SMTxPR; period match interrupt occurs when clocked
0 = Counter resets to 24’h000000; period match interrupt occurs when clocked
WPOL: SMTxWIN Input Polarity Control bit
1 = SMTxWIN signal is active-low/falling edge enabled
0 = SMTxWIN signal is active-high/rising edge enabled
SPOL: SMTxSIG Input Polarity Control bit
1 = SMTx_signal is active-low/falling edge enabled
0 = SMTx_signal is active-high/rising edge enabled
CPOL: SMT Clock Input Polarity Control bit
1 = SMTxTMR increments on the falling edge of the selected clock signal
0 = SMTxTMR increments on the rising edge of the selected clock signal
SMTxPS<1:0>: SMT Prescale Select bits
11 = Prescaler = 1:8
10 = Prescaler = 1:4
01 = Prescaler = 1:2
00 = Prescaler = 1:1
Note 1: Setting EN to ‘0’ does not affect the register contents.
DS40001824A-page 544
Preliminary
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