PIC16LF18854 Datasheet, PDF (39/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
3.2.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
3.2.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2:
BANKED MEMORY
PARTITIONING
7-bit Bank Offset
Memory Region
00h
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(20 bytes maximum)
1Fh
20h
General Purpose RAM
(80 bytes maximum)
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5 DEVICE MEMORY MAPS
The memory maps are as shown in Table 3-3 through
Table 3-13.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 39