PIC16LF18854 Datasheet, PDF (354/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
23.5.1 DIGITAL FILTER/AVERAGE
The digital filter/average module consists of an accu-
mulator with data feedback options, and control logic to
determine when threshold tests need to be applied.
The accumulator is a 16-bit wide signed register
(15 bits + 1 sign bit), which can be accessed through
the ADACCH:ADACCL register pair.
Upon each trigger event (the ADGO bit set or external
event trigger), the ADC conversion result is added to
the accumulator. If the value exceeds
‘1111111111111111’, then the overflow bit ADAOV in
the ADSTAT register is set.
The number of samples to be accumulated is
determined by the ADRPT (A/D Repeat Setting)
register. Each time a sample is added to the
accumulator, the ADCNT register is incremented. In
Average and Burst Average modes the ADCNT and
ADACC registers are cleared automatically when a
trigger causes the ADCNT value to exceed the ADRPT
value to ‘1’ and replace the ADACC contents with the
conversion result.
The ADAOV (accumulator overflow) bit in the ADSTAT
register, ADACC, and ADCNT registers will be cleared
any time the ADACLR bit in the ADCON2 register is
set.
Note:
When ADC is operating from FRC, 5 FRC
clock cycles are required to execute the
ADACC clearing operation.
The ADCRS <2:0> bits in the ADCON2 register control
the data shift on the accumulator result, which
effectively divides the value in the accumulator
(ADACCH:ADACCL) register pair. For the Accumulate
mode of the digital filter, the shift provides a simple
scaling operation. For the Average/Burst Average
mode, the shift bits are used to determine number of
samples for averaging. For the Lowpass Filter mode,
the shift is an integral part of the filter, and determines
the cut-off frequency of the filter. Table 23-4 shows the
-3 dB cut-off frequency in ωT (radians) and the highest
signal attenuation obtained by this filter at nyquist
frequency (ωT = π).
TABLE 23-4: LOWPASS FILTER -3 dB CUT-OFF FREQUENCY
ADCRS
ωT (radians) @ -3 dB Frequency
1
0.72
2
0.284
3
0.134
4
0.065
5
0.032
dB @ F_nyquist=1/(2T)
-9.5
-16.9
-23.5
-29.8
-36.0
23.5.2 BASIC MODE
Basic mode (ADMD= ‘000’) disables all additional
computation features. In this mode, no accumulation
occurs and no threshold error comparison is
performed. Double sampling, continuous mode, and all
CVD features are still available, but no features
involving the digital filter/average features are used.
23.5.3 ACCUMULATE MODE:
In Accumulate mode (ADMD = ‘001’), the ADC
conversion result is right shifted by the value of the
ADCRS bits in the ADCON2 register and added to the
ADACC registers. The Formatting mode does not
affect the right-justification of the ADACC value. Upon
each sample, ADCNT is incremented, indicating the
number of samples accumulated. After each sample
and accumulation, the ADACC value has a threshold
comparison performed on it (see Section 23.5.7
“Threshold Comparison”) and the ADTIF interrupt
may trigger.
23.5.4 AVERAGE MODE
In Average Mode (ADMD = ‘010’), the ADACC
registers accumulate with each ADC sample, much as
in Accumulate mode, and the ADCNT register
increments with each sample. However, in Average
mode, the threshold comparison is performed upon
ADCNT being greater than or equal to a user-defined
ADRPT value. The ADCRS bits still right-shift the final
result, but in this mode when ADCRS=
log(ADRPT)/log(2) then the final accumulated value
will be divided by number of samples, allowing for a
threshold comparison operation on the average of all
gathered samples.
DS40001824A-page 354
Preliminary
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