PIC16LF18854 Datasheet, PDF (591/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 36-4: INSTRUCTION SET
Mnemonic,
Operands
Description
14-Bit Opcode
Cycles
MSb
LSb
Status
Affected
Notes
ADDWF f, d
ADDWFC f, d
ANDWF f, d
ASRF
f, d
LSLF
f, d
LSRF
f, d
CLRF
f
CLRW –
COMF f, d
DECF
f, d
INCF
f, d
IORWF f, d
MOVF f, d
MOVWF f
RLF
f, d
RRF
f, d
SUBWF f, d
SUBWFB f, d
SWAPF f, d
XORWF f, d
DECFSZ ^{f, d}
INCFSZ ^{f, d}
BYTE-ORIENTED FILE REGISTER OPERATIONS
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
00 0111 dfff ffff C, DC, Z 2
1
11 1101 dfff ffff C, DC, Z 2
1
00 0101 dfff ffff Z
2
1
11 0111 dfff ffff C, Z
2
1
11 0101 dfff ffff C, Z
2
1
11 0110 dfff ffff C, Z
2
1
00 0001 lfff ffff Z
2
1
00 0001 0000 00xx Z
1
00 1001 dfff ffff Z
2
1
00 0011 dfff ffff Z
2
1
00 1010 dfff ffff Z
2
1
00 0100 dfff ffff Z
2
1
00 1000 dfff ffff Z
2
1
00 0000 1fff ffff
2
1
00 1101 dfff ffff C
2
1
00 1100 dfff ffff C
2
1
00 0010 dfff ffff C, DC, Z 2
1
11 1011 dfff ffff C, DC, Z 2
1
00 1110 dfff ffff
2
1
00 0110 dfff ffff Z
2
BYTE ORIENTED SKIP OPERATIONS
Decrement f, Skip if 0
Increment f, Skip if 0
1(2) 00 1011 dfff ffff
1, 2
1(2) 00 1111 dfff ffff
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b
BSF
f, b
Bit Clear f
Bit Set f
1
01 00bb bfff ffff
2
1
01 01bb bfff ffff
2
BIT-ORIENTED SKIP OPERATIONS
BTFSC f, b
BTFSS f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2) 01 10bb bfff ffff
1, 2
1 (2) 01 11bb bfff ffff
1, 2
LITERAL OPERATIONS
ADDLW k
ANDLW k
IORLW k
MOVLB k
MOVLP k
MOVLW k
SUBLW k
XORLW k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
1
11 1110 kkkk kkkk C, DC, Z
1
11 1001 kkkk kkkk Z
1
11 1000 kkkk kkkk Z
1
00 0000 001k kkkk
1
11 0001 1kkk kkkk
1
11 0000 kkkk kkkk
1
11 1100 kkkk kkkk C, DC, Z
1
11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
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Preliminary
DS40001824A-page 591