PIC16LF18854 Datasheet, PDF (252/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 14-1: PMD0: PMD CONTROL REGISTER 0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
SYSCMD
FVRMD
—
CRCMD
SCANMD
7
R/W-0/0
NVMMD
R/W-0/0
CLKRMD
R/W-0/0
IOCMD
0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
SYSCMD: Disable Peripheral System Clock Network bit
See description in Section 14.4 “System Clock Disable”.
1 = System clock network disabled (a.k.a. FOSC)
0 = System clock network enabled
bit 6
FVRMD: Disable Fixed Voltage Reference (FVR) bit
1 = FVR module disabled
0 = FVR module enabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CRCMD: CRC module disable bit
1 = CRC module disabled
0 = CRC module enabled
bit 3
SCANMD: Program Memory Scanner Module Disable bit
1 = Scanner module disabled
0 = Scanner module enabled
bit 2
NVMMD: NVM Module Disable bit⁽¹⁾
1 = User memory and EEPROM reading and writing is disabled; NVMCON registers cannot be written;
FSR access to these locations returns zero.
0 = NVM module enabled
bit 1
CLKRMD: Disable Clock Reference CLKR bit
1 = CLKR module disabled
0 = CLKR module enabled
bit 0
IOCMD: Disable Interrupt-on-Change bit, All Ports
1 = IOC module(s) disabled
0 = IOC module(s) enabled
Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.
DS40001824A-page 252
Preliminary
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