PIC16LF18854 Datasheet, PDF (626/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 37-15: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121
US121
DT
Note:
US120
Refer to Figure 37-4 for load conditions.
US122
TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
US120
Symbol
TCKH2DTV
US121 TCKRF
US122 TDTRF
Characteristic
SYNC XMIT (Master and Slave)
Clock high to data-out valid
Clock out rise time and fall time
(Master mode)
Data-out rise time and fall time
Min.
—
—
—
—
—
—
Max.
80
100
45
50
45
50
Units
Conditions
ns 3.0V  VDD  5.5V
ns 1.8V  VDD  5.5V
ns 3.0V  VDD  5.5V
ns 1.8V  VDD  5.5V
ns 3.0V  VDD  5.5V
ns 1.8V  VDD  5.5V
FIGURE 37-16: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
Note: Refer to Figure 37-4 for load conditions.
US126
TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
US125 TDTV2CKL
US126 TCKL2DTL
Characteristic
SYNC RCV (Master and Slave)
Data-setup before CK  (DT hold time)
Data-hold after CK  (DT hold time)
Min.
Max.
10
—
15
—
Units
ns
ns
Conditions
DS40001824A-page 626
Preliminary
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