PIC16LF18854 Datasheet, PDF (90/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
3.5.2 LINEAR DATA MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-10:
LINEAR DATA MEMORY
MAP
7 _FSRnH
0 01
07
FSRnL
0
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Bank 2
0x16F
0xF20
Bank 30
0x29AF ^0xF6F
3.5.3 DATA EEPROM MEMORY
The EEPROM memory can be read or written through
the NVMCONx/NVMADRx/NVMDATx register
interface (see section Section 10.2 “Data EEPROM
Memory”). However, to make access to the EEPROM
memory easier, read-only access to the EEPROM
contents are also available through indirect addressing
by an FSR. When the MSB of the FSR (ex: FSRxH) is
set to 0x70, the lower 8-bit address value (in FSRxL)
determines the EEPROM location that may be read
from (through the INDF register). In other words, the
EEPROM address range 0x00-0xFF is mapped into the
FSR address space between 0x7000-0x70FF. Writing
to the EEPROM cannot be accomplished via the
FSR/INDF interface. Reads from the EEPROM through
the FSR/INDF interface will require one additional
instruction cycle to complete.
3.5.4 PROGRAM FLASH MEMORY
To make constant data access easier, the entire
Program Flash Memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower eight bits of each memory location is accessible
via INDF. Writing to the Program Flash Memory cannot
be accomplished via the FSR/INDF interface. All
instructions that access Program Flash Memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-11:
PROGRAM FLASH
MEMORY MAP
7 _FSRnH
1
07
FSRnL
0
Location Select
0x8000 _0x0000
Program
Flash
Memory
(low 8
bits)
0xFFFF ^0x7FFF
DS40001824A-page 90
Preliminary
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