PIC16LF18854 Datasheet, PDF (135/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-4: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
R/W-0/0
U-0
U-0
U-0
U-0
—
ZCDIE
—
—
—
—
bit 7
R/W-0/0
C2IE
R/W-0/0
C1IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5-2
bit 1
bit 0
Unimplemented: Read as ‘0’
ZCDIE: Zero-Cross Detection (ZCD) Interrupt Enable bit
1 = Enables the ZCD interrupt
0 = Disables the ZCD interrupt
Unimplemented: Read as ‘0’
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 135