PIC16LF18854 Datasheet, PDF (418/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
28.11 Register Definitions: Timer1 Control start here with Memory chapter compare
Long bit name prefixes for the Timer1/3/5 are shown in
Table 28-3. Refer to Section 1.1 “Register and Bit
naming conventions” for more information
TABLE 28-3:
Peripheral
Bit Name Prefix
Timer1
T1
Timer3
T3
Timer5
T5
REGISTER 28-1: TxCON: TIMER1/3/5 CONTROL REGISTER
U-0
—
bit 7
U-0
R/W-0/u
R/W-0/u
U-0
—
CKPS<1:0>
—
R/W-0/u
SYNC
R/W-0/u
RD16
R/W-0/u
ON
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
Unimplemented: Read as ‘0’
SYNC: Timer1 Synchronization Control bit
When TMR1CLK = FOSC or FOSC/4
This bit is ignored. The timer uses the internal clock and no additional synchronization is performed.
When TMR1CS<1:0> = (any setting other than FOSC or FOSC/4)
1 = Do not synchronize external clock input
0 = Synchronized external clock input with system clock
RD16: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
DS40001824A-page 418
Preliminary
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