PIC16LF18854 Datasheet, PDF (180/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
EXAMPLE 10-5: DEVICE ID ACCESS
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
NVMADRH
ADDRH,W
NVMADRH
ADDRL,W
NVMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
NVMCON1,NVMREGS
NVMCON1,WREN
NVMCON1,LWLO
; Load initial address
; Load initial data address
; Set PFM as write location
; Enable writes
; Load only write latches
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
MOVF
XORLW
ANDLW
BTFSC
GOTO
CALL
INCF
GOTO
FSR0++
NVMDATL
FSR0++
NVMDATH
NVMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
UNLOCK_SEQ
NVMADRL,F
LOOP
; Load first data byte
; Load second data byte
; Check if lower bits of address are 00000
; and if on last of 32 addresses
; Last of 32 words?
; If so, go write latches into memory
; If not, go load latch
; Increment address
START_WRITE
BCF
CALL
BCF
NVMCON1,LWLO
UNLOCK_SEQ
NVMCON1,WREN
; Latch writes complete, now write memory
; Perform required unlock sequence
; Disable writes
UNLOCK_SEQ
MOVLW
BCF
MOVWF
MOVLW
MOVWF
BSF
BSF
return
55h
INTCON,GIE
NVMCON2
AAh
NVMCON2
NVMCON1,WR
INTCON,GIE
; Disable interrupts
; Begin unlock sequence
; Unlock sequence complete, re-enable interrupts
DS40001824A-page 180
Preliminary
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