PIC16LF18854 Datasheet, PDF (201/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
12.4.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 12-9) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTA register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 37-4 for more information on threshold
levels.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
12.4.6 ANALOG CONTROL
The ANSELA register (Register 12-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with its TRIS bit clear and its
ANSEL bit set will still operate as a digital output, but
the Input mode will be analog. This can cause
unexpected
behavior
when
executing
read-modify-write instructions on the affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
12.4.7 WEAK PULL-UP CONTROL
The WPUA register (Register 12-6) controls the
individual weak pull-ups for each PORT pin.
12.4.8
CURRENT-CONTROL DRIVE MODE
CONTROL
The CCDPA and CCDNA registers (Register 12-9) and
(Register 12-10) control the Current-Controlled Drive
mode for both the positive-going and negative-going
drivers. When a CCDPA[y] or CCDNA[y] bit is set and
the CCDEN bit of the CCDCON register is set, the
current-controlled mode is enabled for the
corresponding port pin. When the CCDPA[y] or
CCDNA[y] bit is clear, the current-controlled mode for
the corresponding port pin is disabled. If the CCDPA[y]
or CCDNA[y] bit is set and the CCDEN bit is clear,
operation of the port pin is undefined (see
Section 12.1.1 “Current-Controlled Drive”).
12.4.9
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after Reset.
Other output functions are selected with the peripheral
pin select logic or by enabling an analog output, such
as the DAC. See Section 13.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 201