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| PIC16LF18854 Datasheet, PDF (311/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture | |||
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PIC16(L)F18856/76
REGISTER 20-7: CWGxSTR: CWGx STEERING CONTROL REGISTER(1)
R/W-0/0
OVRD
bit 7
R/W-0/0
OVRC
R/W-0/0
OVRB
R/W-0/0
OVRA
R/W-0/0
STRD(2)
R/W-0/0
STRC(2)
R/W-0/0
STRB(2)
R/W-0/0
STRA(2)
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
â1â = Bit is set
W = Writable bit
x = Bit is unknown
â0â = Bit is cleared
U = Unimplemented bit, read as â0â
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
OVRD: Steering Data D bit
bit 6
OVRC: Steering Data C bit
bit 5
OVRB: Steering Data B bit
bit 4
OVRA: Steering Data A bit
bit 3
STRD: Steering Enable D bit(2)
1 = CWGxD output has the CWGx_data waveform with polarity control from POLD bit
0 = CWGxD output is assigned the value of OVRD bit
bit 2
STRC: Steering Enable C bit(2)
1 = CWGxC output has the CWGx_data waveform with polarity control from POLC bit
0 = CWGxC output is assigned the value of OVRC bit
bit 1
STRB: Steering Enable B bit(2)
1 = CWGxB output has the CWGx_data waveform with polarity control from POLB bit
0 = CWGxB output is assigned the value of OVRB bit
bit 0
STRA: Steering Enable A bit(2)
1 = CWGxA output has the CWGx_data waveform with polarity control from POLA bit
0 = CWGxA output is assigned the value of OVRA bit
Note 1: The bits in this register apply only when MODE<2:0> = 00x.
2: This bit is effectively double-buffered when MODE<2:0> = 001.
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 311
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