PIC16LF18854 Datasheet, PDF (33/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
2.0 ENHANCED MID-RANGE CPU
This family of devices contains an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16-levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
FIGURE 2-1:
CORE BLOCK DIAGRAM
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
15
Configuration
15
Data Bus
8
Program Counter
Nonvolatile
Memory
186-LLeevveel lSStatacckk
(135-bit)
RAM
Program
Bus
14
IInnssttrruuccttiioonn Rreegg
15
15
Program Memory
Read (PMR)
12 ^{RAM Addr}
Addr MUX
Direct Addr ⁷
8
Indirect
Addr
5
12
12
BFSSRR Rreegg
FSR0reRgeg
FFSSRR1 rReegg
SSTTAATTUUSSRreegg
OSC1/CLKIN
OSC2/CLKOUT
Instruction
DDeeccooddeea&nd
Control
Timing
Generation
Internal
Oscillator
Block
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
3
MUX
ALU
8
W reg
VDD VSS
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 33