PIC16LF18854 Datasheet, PDF (24/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Name
Function
Input
Type
Output Type
Description
VSS
OUT⁽²⁾
VSS
ADGRDA
Power
—
—
CMOS/OD
Ground reference.
ADC Guard Ring A output.
ADGRDB
—
CMOS/OD ADC Guard Ring B output.
C1OUT
—
CMOS/OD Comparator 1 output.
C2OUT
—
CMOS/OD Comparator 2 output.
SDO1
—
CMOS/OD
MSSP1 SPI serial data output.
SCK1
—
CMOS/OD
MSSP1 SPI serial clock output.
SDO2
—
CMOS/OD
MSSP2 SPI serial data output.
SCK2
—
CMOS/OD
MSSP2 SPI serial clock output.
TX
CK⁽³⁾
DT⁽³⁾
—
CMOS/OD EUSART Asynchronous mode transmitter data output.
—
CMOS/OD EUSART Synchronous mode clock output.
—
CMOS/OD EUSART Synchronous mode data output.
DSM
—
CMOS/OD Data Signal Modulator output.
TMR0
—
CMOS/OD Timer0 output.
CCP1
—
CMOS/OD Capture/Compare/PWM1 output (compare/PWM functions).
CCP2
—
CMOS/OD Capture/Compare/PWM2 output (compare/PWM functions).
CCP3
—
CMOS/OD Capture/Compare/PWM3 output (compare/PWM functions).
CCP4
—
CMOS/OD Capture/Compare/PWM4 output (compare/PWM functions).
CCP5
—
CMOS/OD Capture/Compare/PWM5 output (compare/PWM functions).
PWM6OUT
—
CMOS/OD PWM6 output.
PWM7OUT
—
CMOS/OD PWM7 output.
CWG1A
—
CMOS/OD Complementary Waveform Generator 1 output A.
CWG1B
—
CMOS/OD Complementary Waveform Generator 1 output B.
CWG1C
—
CMOS/OD Complementary Waveform Generator 1 output C.
CWG1D
—
CMOS/OD Complementary Waveform Generator 1 output D.
CWG2A
—
CMOS/OD Complementary Waveform Generator 2 output A.
CWG2B
—
CMOS/OD Complementary Waveform Generator 2 output B.
CWG2C
—
CMOS/OD Complementary Waveform Generator 2 output C.
CWG2D
—
CMOS/OD Complementary Waveform Generator 2 output D.
CWG3A
—
CMOS/OD Complementary Waveform Generator 3 output A.
CWG3B
—
CMOS/OD Complementary Waveform Generator 3 output B.
Legend: AN = Analog input or output
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
OD = Open-Drain
I²C = Schmitt Trigger input with I²C
HV = High Voltage
XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I²C specific or SMBus input buffer thresholds.
DS40001824A-page 24
Preliminary
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