PIC16LF18854 Datasheet, PDF (328/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 22-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-0/0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
LCxPOL
—
—
—
LCxG4POL LCxG3POL
bit 7
R/W-x/u
LCxG2POL
R/W-x/u
LCxG1POL
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
LCxPOL: CLCxOUT Output Polarity Control bit
1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
Unimplemented: Read as ‘0’
LCxG4POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
LCxG3POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
LCxG2POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted
LCxG1POL: Gate 0 Output Polarity Control bit
1 = The output of gate 0 is inverted when applied to the logic cell
0 = The output of gate 0 is not inverted
DS40001824A-page 328
Preliminary
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