PIC16LF18854 Datasheet, PDF (569/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 33-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 7
Word 1
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
Write Word 1
TRMT bit
Write Word 2
bit 0
bit 1
Word 2
TXEN bit ^{‘1’}
Note:
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 33-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
bit 7
‘1’
TRMT bit
TXEN bit
33.4.1.5 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RC1STA register) or the Continuous Receive Enable
bit (CREN of the RC1STA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 569