PIC16LF18854 Datasheet, PDF (158/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 8-2: CPUDOZE: DOZE AND IDLE REGISTER
R/W-0/u
R/W/HC/HS-0/0
R/W-0/0
R/W-0/0
U-0
IDLEN
DOZEN^(1,2)
ROI
DOE
—
bit 7
R/W-0/0
R/W-0/0
DOZE<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
IDLEN: Idle Enable bit
1 = A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)
0 = A SLEEP instruction places the device into full Sleep mode
DOZEN: Doze Enable bit^(1,2)
1 = The CPU executes instruction cycles according to DOZE setting
0 = The CPU executes all instruction cycles (fastest, highest power operation)
ROI: Recover-on-Interrupt bit
1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed operation.
0 = Interrupt entry does not change DOZEN
DOE: Doze on Exit bit
1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation.
0 = RETFIE does not change DOZEN
Unimplemented: Read as ‘0’
DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
111 = 1:256
110 = 1:128
101 = 1:64
100 = 1:32
011 = 1:16
010 = 1:8
001 = 1:4
000 = 1:2
Note 1: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.
DS40001824A-page 158
Preliminary
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