PIC16LF18854 Datasheet, PDF (168/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
10.0 NONVOLATILE MEMORY
(NVM) CONTROL
NVM is separated into two types: Program Flash
Memory (PFM) and Data EEPROM Memory.
NVM is accessible by using both the FSR and INDF
registers, or through the NVMREG register interface.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the operating
voltage range of the device.
NVM can be protected in two ways; by either code
protection or write protection.
Code protection (CP and CPD bits in Configuration
Word 5) disables access, reading and writing, to both
the PFM and EEPROM via external device program-
mers. Code protection does not affect the self-write and
erase functionality. Code protection can only be Reset
by a device programmer performing a Bulk Erase to the
device, clearing all nonvolatile memory, Configuration
bits, and User IDs.
Write protection prohibits self-write and erase to a
portion or all of the PFM, as defined by the WRT<1:0>
bits of Configuration Word 4. Write protection does not
affect a device programmer’s ability to read, write, or
erase the device.
10.1 Program Flash Memory (PFM)
PFM consists of an array of 14-bit words as user
memory, with additional words for User ID information,
Configuration words, and interrupt vectors. PFM
provides storage locations for:
• User program instructions
• User defined data
PFM data can be read and/or written to through:
• CPU instruction fetch (read-only)
• FSR/INDF indirect access (read-only)
(Section 10.3 “FSR and INDF Access”)
• NVMREG access (Section 10.4 “NVMREG
Access”
• In-Circuit Serial Programming™ (ICSP™)
Read operations return a single word of memory. When
write and erase operations are done on a row basis, the
row size is defined in Table 10-1. PFM will erase to a
logic ‘1’ and program to a logic ‘0’.
TABLE 10-1: FLASH MEMORY
ORGANIZATION BY DEVICE
Device
Row Erase
(words)
Write
Latches
(words)
Total
Program
Flash
(words)
PIC16(L)F18856
PIC16(L)F18876
32
32
16384
It is important to understand the PFM memory structure
for erase and programming operations. PFM is
arranged in rows. A row consists of 32 14-bit program
memory words. A row is the minimum size that can be
erased by user software.
After a row has been erased, all or a portion of this row
can be programmed. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These latches are not directly accessible, but
may be loaded via sequential writes to the
NVMDATH:NVMDATL register pair.
Note:
To modify only a portion of a previously
programmed row, then the contents of the
entire row must be read and saved in
RAM prior to the erase. Then, the new
data and retained data can be written into
the write latches to reprogram the row of
PFM. However, any unprogrammed
locations can be written without first
erasing the row. In this case, it is not
necessary to save and rewrite the other
previously programmed locations
10.1.1 PROGRAM MEMORY VOLTAGES
The PFM is readable and writable during normal
operation over the full VDD range.
10.1.1.1 Programming Externally
The program memory cell and control logic support
write and Bulk Erase operations down to the minimum
device operating voltage. Special BOR operation is
enabled during Bulk Erase (Section 5.2.4 “BOR is
always OFF”).
10.1.1.2 Self-programming
The program memory cell and control logic will support
write and row erase operations across the entire VDD
range. Bulk Erase is not supported when self-
programming.
DS40001824A-page 168
Preliminary
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