PIC16LF18854 Datasheet, PDF (618/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 37-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-up Time
Internal Reset⁽¹⁾
Watchdog Timer
Reset⁽¹⁾
RST04
RST05
I/O pins
Note 1: Asserted low.
RST01
RST02
RST03
RST02
FIGURE 37-9:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR and VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33⁽¹⁾
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms
delay if PWRTE = 0.
DS40001824A-page 618
Preliminary
 2016 Microchip Technology Inc.