PIC16LF18854 Datasheet, PDF (144/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-13: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
R/W/HS-0/0
U-0
U-0
U-0
U-0
R/W/HS-0/0
—
ZCDIF
—
—
—
—
C2IF
bit 7
R/W/HS-0/0
C1IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
bit 6
bit 5-2
bit 1
bit 0
Unimplemented: Read as ‘0’
ZCDIF: Zero-Cross Detect (ZCD) Interrupt Flag bit
1 = An enabled rising and/or falling ZCD event has been detected (must be cleared in software)
0 = No ZCD event has occurred
Unimplemented: Read as ‘0’
C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator 2 interrupt asserted (must be cleared in software)
0 = Comparator 2 interrupt not asserted
C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator 1 interrupt asserted (must be cleared in software)
0 = Comparator 1 interrupt not asserted
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001824A-page 144
Preliminary
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