PIC16LF18854 Datasheet, PDF (154/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
8.1.2 INTERRUPTS DURING DOZE
If an interrupt occurs and the Recover-On-Interrupt bit
is clear (ROI = 0) at the time of the interrupt, the
Interrupt Service Routine (ISR) continues to execute at
the rate selected by DOZE<2:0>. Interrupt latency is
extended by the DOZE<2:0> ratio.
If an interrupt occurs and the ROI bit is set (ROI = 1) at
the time of the interrupt, the DOZEN bit is cleared and
the CPU executes at full speed. The prefetched instruc-
tion is executed and then the interrupt vector sequence
is executed. In Figure 8-1, the interrupt occurs during
the 2^nd instruction cycle of the Doze period, and imme-
diately brings the CPU out of Doze. If the Doze-On-Exit
(DOE) bit is set (DOE = 1) when the RETFIE operation
is executed, DOZEN is set, and the CPU executes at
the reduced rate based on the DOZE<2:0> ratio.
8.2 Sleep Mode
Sleep mode is entered by executing the SLEEP
instruction, while the Idle Enable (IDLEN) bit of the
CPUDOZE register is clear (IDLEN = 0). If the SLEEP
instruction is executed while the IDLEN bit is set
(IDLEN = 1), the CPU will enter the IDLE mode
(Section 8.2.3 “Low-Power Sleep Mode”).
Upon entering Sleep mode, the following conditions
exist:
1. WDT will be cleared but keeps running if
enabled for operation during Sleep
2. The PD bit of the STATUS register is cleared
3. The TO bit of the STATUS register is set
4. The CPU clock is disabled
5. 31 kHz LFINTOSC, HFINTOSC and SOSC are
unaffected and peripherals using them may
continue operation in Sleep.
6. Timer1 and peripherals that use it continue to
operate in Sleep when the Timer1 clock source
selected is:
• LFINTOSC
• T1CKI
• Secondary Oscillator
7. ADC is unaffected if the dedicated FRC
oscillator is selected
8. I/O ports maintain the status they had before
Sleep was executed (driving high, low, or
high-impedance)
9. Resets other than WDT are not affected by
Sleep mode
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
- I/O pins should not be floating
- External circuitry sinking current from I/O pins
- Internal circuitry sourcing current from I/O
pins
- Current draw from pins with internal weak
pull-ups
- Modules using any oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 25.0 “5-Bit Digital-to-Analog
Converter (DAC1) Module” and 16.0 “Fixed Voltage
Reference (FVR)” for more information on these
modules.
8.2.1 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin, if enabled.
2. BOR Reset, if enabled.
3. POR Reset.
4. Watchdog Timer, if enabled.
5. Any external interrupt.
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information).
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to Section 5.11
“Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes-up from
Sleep, regardless of the source of wake-up.
DS40001824A-page 154
Preliminary
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