PIC16LF18854 Datasheet, PDF (26/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION
Name
RA0/ANA0/C1IN0-/C2IN0-/
CLCIN0⁽¹⁾/IOCA0
Function
RA0
ANA0
Input Type Output Type
Description
TTL/ST CMOS/OD
General purpose I/O.
AN
—
ADC Channel A0 input.
C1IN0-
AN
—
Comparator negative input.
C2IN0-
CLCIN0⁽¹⁾
AN
TTL/ST
—
Comparator negative input.
—
Configurable Logic Cell source input.
IOCA0
TTL/ST
—
Interrupt-on-change input.
RA1/ANA1/C1IN1-/C2IN1-/
CLCIN1⁽¹⁾/IOCA1
RA1
ANA1
TTL/ST
AN
CMOS/OD
—
General purpose I/O.
ADC Channel A1 input.
C1IN1-
AN
—
Comparator negative input.
C2IN1-
CLCIN1⁽¹⁾
AN
TTL/ST
—
Comparator negative input.
—
Configurable Logic Cell source input.
IOCA1
TTL/ST
—
Interrupt-on-change input.
RA2/ANA2/C1IN0+/C2IN0+/VREF-/
DAC1OUT1/IOCA2
RA2
ANA2
TTL/ST
AN
CMOS/OD
—
General purpose I/O.
ADC Channel A2 input.
C1IN0+
AN
—
Comparator positive input.
C2IN0+
AN
—
Comparator positive input.
VREF-
AN
DAC1OUT1
—
—
External ADC and/or DAC negative reference input.
AN
Digital-to-Analog Converter output.
IOCA2
TTL/ST
—
Interrupt-on-change input.
RA3/ANA3/C1IN1+/VREF+/
MDCARL⁽¹⁾/IOCA3
RA3
ANA3
TTL/ST
AN
CMOS/OD
—
General purpose I/O.
ADC Channel A3 input.
C1IN1+
AN
—
Comparator positive input.
VREF+
MDCARL⁽¹⁾
AN
TTL/ST
—
External ADC and/or DAC positive reference input.
—
Modular Carrier input 1.
RA4/ANA4/MDCARH⁽¹⁾/T0CKI⁽¹⁾/
CCP5⁽¹⁾/IOCA4
IOCA3
RA4
ANA4
MDCARH⁽¹⁾
T0CKI⁽¹⁾
CCP5⁽¹⁾
IOCA4
TTL/ST
TTL/ST
AN
TTL/ST
TTL/ST
TTL/ST
—
CMOS/OD
—
—
—
CMOS/OD
TTL/ST
—
Interrupt-on-change input.
General purpose I/O.
ADC Channel A4 input.
Modular Carrier input 2.
Timer0 clock input.
Capture/compare/PWM5 (default input location for capture
function).
Interrupt-on-change input.
Legend: AN = Analog input or output
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
OD = Open-Drain
I²C = Schmitt Trigger input with I²CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I²C specific or SMBus input buffer thresholds.
DS40001824A-page 26
Preliminary
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